The present invention relates to a microprocessor, especially to one suitable for three-dimensional graphic processing.
There are several kinds of three-dimensional graphic processings. For example, in glow shading processing, interpolation calculation is carried out. FIG. 7 shows the variation of the bit number of data used in this calculation. Assuming that data showing brightness in the point n is I.sub.n, a brightness I.sub.n+1 in the point n+1 is obtained by adding the increment .DELTA.I between these points to I.sub.n.
This applies also to the case of hidden surface processing. Hidden surface processing is processing to cancel surfaces invisible from a certain viewing point, and data Z indicating a depth of each point are then used. Also regarding the depth Z, the increment .DELTA.Z is added to the value Z.sub.n indicating the depth at the point n so that the depth Z.sub.n+1 can be obtained.
Here, data of the brightness I.sub.n or the depth Z.sub.n are expressed by an integer. But operations are carried out with a double accuracy fixed decimal point with a length of 64 bits in total, having e.g., a fraction part of 32 bits length being the same as the integer so that cumulative errors may not occur at the time of addition. As the ultimate results after addition, only 32 bits of the integer part among 64 bits are taken and written into a memory.
When color processing is carried out, information of each of the colors of red (R), green (G) and blue (B) is expressed by an integer having a length of 8 bits generally as shown in FIG. 8. But, since double accuracy is necessary to carry out the interpolation calculation as described above, each requires 2.times.16 bits, that is, 48 bits are required as a whole. After the addition, the integer parts each having a length of 8 bits are extracted individually and stored in the memory.
As a microprocessor carrying out three-dimensional graphic processings in the prior art, there is, for example, the microprocessor 80860 disclosed in Nikkei Electronics, Apr. 3, 1989 (No. 470) pp. 199-209. This microprocessor has an integer processing unit (hereinafter referred to as "IPU") at an integer processing section, a floating point processing unit (hereinafter referred to as "FPU") at a floating point processing section, and a register file (hereinafter referred to as "RF") at each of the processing sections.
The register file of the integer processing section has 32 bits, and the register file of the floating point processing section has 64 bits. For color processing requiring 48 bits, the register file of the integer processing section has an insufficient bit number and therefore the register file of the floating point processing section of 64 bits is used. Consequently, in order to make such a microprocessor have the three-dimensional processing function, an arithmetic device for carrying out addition or the like at the FPU side takes the form of holding the register file jointly between the FPU and the arithmetic device.
FIG. 9 shows the constitution of a microprocessor at an FPU side in the prior art. The microprocessor has an FPU1 92 and an FPU2 93 as FPUs, and a three-dimensional processing unit (hereinafter referred to as "3D unit") 94. These three arithmetic devices have an RF 91 jointly. The RF 91 is provided with source ports S1 and S2 for reading data, and a destination port D for writing data, which are connected to the FPU1 92, the FPU2 93 and the 3D unit 94 respectively. In this case, each of the three ports has 64 bits.
Constitution of the 3D unit 94 among these units is shown in FIG. 10. The input end of a pipeline register 101 for temporarily storing data read out from the source ports S1 and S2 is connected to these ports, and the input end of a partitioned length adder 102 for receiving the stored data and for adding them is connected to an output end of the pipeline register 101. The output end of the partitioned length adder 102 is connected to an input end of a temporary register 105 for temporarily storing the addition results and an input end of a selector (hereinafter referred to as "SEL") 103 respectively. The output end of the temporary register 105 is connected to the input end of a shifter 106 for receiving the stored data and data given from a merge register and for shifting the data in sequence. The output end of the shifter 106 is connected to an input end of a merge register 107 for collecting and consolidating different data into one data. The output end of the merge register 107 is connected to an input end of the shifter 106 and an input end of the SEL 103, and an output end of the SEL 103 is connected to a pipeline register 104. The output end of the pipeline register 104 is connected to the destination port D of the RF 91.
The 3D unit 94 operates as follows. Each data R.sub.n, G.sub.n and B.sub.n of 64 bits at the point n being read out from the source ports S1 and S2 of the RF 91 are once stored to the pipeline register 101, and then given to the partitioned length adder 102. At the partitioned length adder 102, the increment .DELTA. of each color is added to the data R.sub.n, G.sub.n and B.sub.n respectively, and data R.sub.n+1, G.sub.n+1 and B.sub.n+1 of 64 bits at the point n+1 are obtained and supplied to the temporary register 105 and the SEL 103. In this case, the increment .DELTA. corresponds to the difference of data between the point n and the point n+1, divided by the number of lattice points to be plotted between the two points.
The SEL 103 changes the output from the merge register 107 and the output from the partitioned length adder 102, and in this case the changing is effected so that the output from the partitioned length adder 102 is outputted to the pipeline register 104. The outputted data at the point n+1 are once stored in the pipeline register 104, and then written into the RF 91 from the destination port D.
The data at the point n+1 outputted from the partitioned length adder 102 are stored once in the temporary register 105, and then given to the shifter 106. The data of 32 bits of the integer part among the data of 64 bits are taken out by the shifter 106, and supplied to the merge register 107.
In the merge register 107, the data R.sub.n-1, G.sub.n-1 and B.sub.n-1 at the point n-1 obtained by the last-before addition and the data R.sub.n, G.sub.n and B.sub.n at the point n obtained by the last addition are stored as one data in the consolidated form respectively as shown in FIG. 11(a). As 32 bits are sufficient for the data of one picture element, the last operation result and the present operation result are stored in combined form.
The data R.sub.n-1, G.sub.n-1 and B.sub.n-1 at the point n-1 are removed by the shifter 106, and the data R.sub.n, G.sub.n and B.sub.n at the point n are shifted to the positions where the above data were stored as shown in FIG. 11(b), and the data R.sub.n+1, G.sub.n+1 and B.sub.n+1 at the point n+1 obtained by the present addition are stored in the positions where the data at the point n existed. The data at the point n and the point n+1 combined in this way are once stored in the merge register 107 and outputted to the SEL 103, and stored in the pipeline register 104 and then outputted to the RF 91. The data stored in the RF 91 are outputted to a memory (not shown).
However, the microprocessor in the prior art has problems the following. In order that the data of two picture elements at the point n and the point n+1 are received and stored in the memory (not shown), every time the data for one picture element are obtained, they must be stored once in the RF 91. For the above, three cycles, that is, the cycle for carrying out addition to obtain data of the point n and for storing data of the point n in the RF 91, the cycle for carrying out addition to obtain data of the point n+1, and the cycle for storing the obtained data of the point n and the point n+1 in the memory are necessary, which hinders high speed processing.
Also in three-dimensional graphical processing, in addition to the above-mentioned glow shading processing and the hidden surface processing, a processing named texture mapping exists. This is a processing to affix a certain diagram indicated by a two-dimensional plane to a surface of a three-dimensional body. In this case, a processing of coordinate transformation or the like is necessary to project the two-dimensional diagram on the surface of the three-dimensional body. The color of the surface of the three-dimensional body becomes ultimately the combination of color of the body itself and color of the diagram being affixed. Therefore the product of data of each color (R, G, B) for each picture element must be searched.
However, the floating point processing section of the microprocessor in the prior art is not provided with the integer multiplication function, and multiplication must be carried out in the integer processing section. If the multiplication of data of 32 bits is carried out by using the Booth algorithm, in the integer processing section, about 11 cycles are needed. Further, data showing three colors (R, G, B) at a certain point cannot be obtained by multiplication once in the processing in the prior art. It is necessary to carry out the peak processing in that multiplication for each color individually and store results once in three registers, and the three multiplication results obtained are then merged to one data and stored in one register. Since several cycles are required additionally for the above pack processing itself, the total cycles become not less than 33 cycles, thereby requiring an enormous time.